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Bit Error Rate Tester
Applications
- LAN/SONET/SDH Component Development
- Satellite System Training
- Digital Transmission System Design
- Fibre Channel Testing
- Uncompressed Digital Video
- High-speed ATM Margin Testing
- Parallel-to-Serial Analysis with MB100
Features
- Operating Frequency Range 700 Mb/s
- Internal PLL Synthesized Clock Source
- PRBS 2n-1; n = 7, 15, 17, 20, 23
- 128 Kbit Programmable Pattern Memory
- Auto-synchronization
- Clock/Data Delay 4 ns, 20 ps Resolution
- TTL, ECL and PECL I/0 Compatible
- Reference Data Input for Proprietary Framed Data
- Pattern Editor (Windows-based) for Custom Word Patterns
- Reference Data Input for Proprietary Framed Data
- Phase Synchronous Clock and Data Edge Tracking
- Supports BURST Mode Operation
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