The Keysight 16550A is part of a new generation of general-purpose logic analyzers. The 16550A module is used with the Keysight 16500B/C mainframe, which is designed as a stand-alone instrument for use by digital and microprocessor hardware and software designers. The 16500B/C mainframe has HP-IB and RS-232-C interfaces for hard copy printouts and control by a host computer.
The 16550A State/Timing Analyzer module has 96 data channels, and six clock/data channels. A second 16550A card can be added to expand the module to 204 data and clock/data channels. Memory depth is 4 Kbytes in all pod pair groupings, or 8 Kbytes on just one pod (half channels). All resource terms can be assigned to either configured analyzer machine.
The 100-MHz state analyzer has master, slave, and demultiplexed clocking modes available. Measurement data can be stamped with either state or time tags. For triggering and data storage, the state analyzer uses 12 sequence levels with two-way branching, 10 pattern resource terms, 2 range terms, and 2 timers/counters.
|Maximum State Speed ||100 MHz |
|Minimum State Clock Pulse Width ||3.5 ns |
|Minimum Master to Master Clock Time1 ||10.0 |
|Minimum Glitch Width ||3.5 ns |
|Threshold Accuracy ||± (100 mV + 3% of threshold setting) |
|Single Clock, Single Edge ||0/3.5 ns through 3.5/0 ns, adjustable in 500 ps increments |
|Single Clock, Multiple Edges ||0.0/4.0 ns through 4.0/0.0 ns, adjustable in 500 ps intervals |
|Multiple Clocks, Multiple Edges ||0.0/4.5 ns through 4.5/0.0 ns, |