Two independent channels available as baseband or IF outputs:
- CH1: Single-ended and differential
- CH2: Single-ended and differential
500 MHz per channel (1 GHz I/Q bandwidth)
15 bits (1/32,768 levels)
Output spectral purity— (CH1 and CH2)
- Harmonic distortion: ≤ -65 dBc for each channel DC to 500 MHz
- Non-harmonic spurious: ≤ -75 dBc for each channel 1 kHz to 500 MHz
- Noise floor: ≤ -150 dBc/Hz across the channel bandwidth
Sample clock Internal
Fixed 1.25 GS/s Internal clock output +3 dBm nominal External clock input Tunable 100 MS/s to 1.25 GS/s External clock input drive level +5 to –15 dBm typical Phase noise characteristics: 1 kHz: -95 dBc/Hz 10 kHz: -115 dBc/Hz 100 kHz: -138 dBc/Hz 1 MHz: -150 dBc/Hz Noise Floor -150 dBc/Hz Accuracy Same as 10 MHz timebase input
Frequency reference Input drive level
+2 to +12 dBm into 50 ohms (+2 dBm nominal)
8 MS per channel (16 MS with Option 016) Minimum waveform length 128 samples Waveform granularity 8 samples
1 to 32 k unique segments can be defined consisting of waveform start and stop address, repetitions, and marker enable flags.
A total of 1 million (220) loops can be defined for each segment. Loops can be configured to advance in one of three modes:
- Single The segment loop plays once and waits at the end of the loop for a trigger.
- Continuous Segment loop is repeated continuously until a trigger is received.
- Auto Automatically advances to the next segment after completing the specified number of loop repetitions.
- Repeat The waveform loop repeats until the number of waveform loop repetitions is met.
Up to 32 k total unique waveform sequences can be defined. A sequence is a contiguous series of waveform segments.
Enables users to build and playback scenarios, which are comprised of one or more sequences.
1 to 16 k pointers can be assigned to play pre-defined sequences. Sequence play begins with the first sequence entry and continues uninterrupted until the last entry is played. The table repeats until stopped.
Sequence jump modes
Sequence jumps determine how a sequence responds to a jump trigger. There are no discontinuities in a sequence jump other than those imposed by the waveform data.
Three modes are available to control sequence jumps:
- Jump immediate: Jumps immediately to the next specified sequence address with a fixed latency.
- End of segment: The current segment (including waveform repeats) is completed before jumping to a new sequence.
- End of sequence: The current sequence is completed before jumping to a new sequence. Jump latency is the longer of either the jump immediate latency or the length of the remaining sequence.
- Dynamic Sequencing (Option 300) Input: 20-pin mini-D connector.
|EXTERNAL TRIGGERS ||EXTERNAL MARKERS |
|Number of inputs ||Markers can be defined for each |
|8 each (4 SMB female front-panel connectors plus four software triggers over the PCI backplane from host processor) ||waveform segment. |
|Trigger polarity Negative/positive ||Number of outputs 4 each SMB female |
|Trigger impedance 2 k ohms ||Marker polarity Negative, positive |
|Maximum input level ±4.5 volts ||Output impedance 50 ohms |
|Input sensitivity 250 mV ||Marker low level 100 mV nominal into high impedance |
|Trigger threshold -4.3 volts to +4.3 volts ||load |
|Trigger timing resolution Clock/8 (6.4 ns at full rate) ||Marker high level |
|Trigger latency 34 * Clk/8 (217.6 ns at full rate) ||3.2 Volts nominal into high impedance load |
|Trigger uncertainty ||Marker timing resolution |
|< 50 ps ||Clock/8 (6.4 ns at full rate) |
|Minimum trigger width ||Marker latency |
|12.8 ns at full clock rate ||Marker precedes analog output and |
|Trigger delay ||is adjustable in 2 sample clock period |
|Programmable from 1 to 256 sync ||steps. |
|clock cycles with 1 sync clock cycle ||Marker latency repeatability |
|resolution ||< 100 ps |
|Module synchronization ||Marker width |
|Supports system scaling for any ||Programmable from 1 to 256 sync |
|number of N6030A modules. A ||clock cycles |
|single module can support fan-out ||Marker delay |
|of 8 N6030A modules for precise ||Programmable from –8 to 502 sample |
|triggering and repeatability. Driver ||clock cycles, with 2 sample clock |
|boards may be used to scale any ||cycle resolution |
|number of modules. |
- Sync clock output level 800 mV p-p (50 ohms, AC coupled)
- Sync clock input sensitivity 100 mV p-p minimum into 50 ohms AC coupled
- Analog output
- Output connector SMA female
- Output impedance 50 Ohms
Analog output levels
The following output levels are specified into 50 ohms.
|Single-ended ||Differential |
|Passive mode ||0.5 Vp-p ||N/A |
|Active mode ||1 Vp-p with ||N/A |
| ||±0.2 V offset || |
|Direct DAC ||N/A ||1 Vp-p |
|mode ||(0 volt offset) |
- Uncorrected passband flatness ±1 dB DC - 200 MHz; ±2.5 dB DC - 500 MHz (with 1.25 GHz clock)
- Uncorrected passband group delay ±500 ps DC - 200 MHz; ±1 ns DC - 500 MHz (with 1.25 GHz clock)
- Reconstruction filters 500 MHz and 250 MHz realized as 7-pole Cauer Chebychev filters plus thru-line output
- Pulse response Rise time (10 to 90%): < 1 ns Fall time (10 to 90%): < 1 ns Amplitude: 0.5 Vp-p